Modern devices may include multiple integrated circuits that are expected to communicate with each other at a very high frequency.
An integrated circuit can be tested at a very low frequency by using a test access port. FIG. 1 illustrates a prior art integrated circuit 9 that includes IO pins 28. An I/O pad 28 can receive information from JTAG compliant boundary scan cells.
JTAG (also known as IEEE standard 1149.1) was designed in order to test integrated circuits. The IEEE standard 1149.1 defines a test access port (TAP) 9 that may be used to access internal components of an integrated circuit. The TAP includes a boundary scan register 30, a one-bit long bypass register 12, an instruction register 18, a TAP controller 20, and an optional user defined data register 14.
TAP 9 receives various signals including a clock signal TCK, a test data input signal TDI, a test mode select signal TMS. The TAP can output a test data output signal TDO. Various control signals provided by the TAP controller 20, especially in response to TMS signals, select a path between the TDI and TDO ports of TAP 9.
The instruction register 18 forms an instruction path while each of the boundary scan register 30, bypass register 12 and the optional user defined data register 14 defines a data path. Each data path and instruction path can be regarded as an internal test path of the TAP.
The TAP controller 20 is a state machine that can apply many stages, including various IEEE standard 1149.1 mandatory states. These mandatory states are controlled by the TMS signal.
FIG. 2 illustrates the multiple states of TAP controller 20, which include test logic reset 40, run-test/idle 41, select DR scan 42, capture DR 43, shift DR 44, exit1 DR 45, pause DR 46, exit2 DR 47, update DR 48, select IR scan 52, capture IR 53, shift IR 54, exit1 IR 55, pause IR 56, exit2 IR 57 and update IR 58. The stages are illustrated as boxes that are linked to each other by arrows. The arrows are accompanied by digits (either 0 or 1) that illustrate the value of the TMS signal. These stages are well known in the art and require no further explanation.
Generally, TAP controller 20 sends control signals that allow to serially input information into selected data and instruction paths, to retrieve information from said paths and to serially propagate (shift) information along data and instruction paths.
JTAG is not adapted to test the connectivity between two devices that are expected to communicate with each other at a high frequency.